Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)MOVNTQMove Non-TemporalQuadword3SSE,MMXExtensionsMOVQ Move Quadword 3 SSE2 MMXMOVQ2DQMove Quadword toQuadwordMOVS Move String 3 BasicMOVSB Move String Byte 3 BasicMOVSD Move String Doubleword 3 Basic 2MOVSDMOVSHDUPMOVSLDUPMove Scalar Double-Precision Floating-PointMove Single-PrecisionHigh and DuplicateMove Single-PrecisionLow and Duplicate3 SSE2 SSE23 SSE2 2MOVSQ Move String Quadword 3 Long ModeMOVSSMove Scalar Single-Precision Floating-PointMOVSW Move String Word 3 BasicMOVSX Move with Sign-Extend 3 BasicMOVSXDMOVUPDInstructionMnemonic Description CPLMove with Sign-ExtendDoublewordMove Unaligned PackedDouble-PrecisionFloating-Point33333General-PurposeLong ModeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE3SSE3SSESSE264-BitMediax87System1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 477