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AMD64 Technology 24594 Rev. 3.10 February 2005CLTSClear Task-Switched Flag in CR0Clears the task-switched (TS) flag in the CR0 register to 0. The processor sets the TSflag on each task switch. The CLTS instruction is intended to facilitate thesynchronization of FPU context saves during multitasking operations.This instruction can only be used if the current privilege level is 0.See “System-Control Registers” in Volume 2 for more information on FPUsynchronization and the TS flag.Mnemonic Opcode DescriptionCLTS 0F 06 Clear the task-switched (TS) flag in CR0 to 0.Related InstructionsLMSW, MOV (CRn)rFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.302 CLTS
24594 Rev. 3.10 February 2005 AMD64 TechnologyHLTHaltCauses the microprocessor to halt instruction execution and enter the HALT state.Entering the HALT state puts the processor in low-power mode. Execution resumeswhen an unmasked hardware interrupt (INTR), non-maskable interrupt (NMI), systemmanagement interrupt (SMI), RESET, or INIT occurs.If an INTR, NMI, or SMI is used to resume execution after a HLT instruction, the savedinstruction pointer points to the instruction following the HLT instruction.Before executing a HLT instruction, hardware interrupts should be enabled. IfrFLAGS.IF = 0, the system will remain in a HALT state until an NMI, SMI, RESET, orINIT occurs.If an SMI brings the processor out of the HALT state, the SMI handler can decidewhether to return to the HALT state or not. See Volume 2, System Programming, forinformation on SMIs.Current privilege level must be 0 to execute this instruction.Mnemonic Opcode DescriptionHLT F4 Halt instruction execution.Related InstructionsSTI, CLIrFLAGS AffectedNoneExceptionsExceptionGeneral protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.HLT 303
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