Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 Technology• 01h—Direct mapped.• 02h through FEh—The value represents the actual associativity. For example, avalue of 04h indicates 4-way associativity.• FFh—Fully associative.Table 3-9.RegisterCPUID TLB Bits for 2-Mbyte and 4-Mbyte Pages (Extended Function 8000_0005—EAX)Data TLBInstruction TLBAssociativity Number of Entries 1 Associativity Number of Entries 1EAX Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0Note:1. The number of entries returned is the number of entries available for the 2-Mbyte page size. The 4-Mbyte pages may require two2-Mbyte entries, depending on the implementation, so the number of entries available for the 4-Mbyte page size would be onehalfthe returned value.Table 3-10.RegisterCPUID TLB Bits for 4-Kbyte Pages (Extended Function 8000_0005—EBX)Data TLBInstruction TLBAssociativity Number of Entries Associativity Number of EntriesEBX Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0Table 3-11.RegisterCPUID L1 Data Cache Bits (Extended Function 8000_0005—ECX)L1 Data CacheSize (Kbytes) Associativity Lines Per Tag Line Size (Bytes)ECX Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0Table 3-12.RegisterCPUID L1 Instruction Cache Bits (Extended Function 8000_0005—EDX)L1 Instruction CacheSize (Kbytes) Associativity Lines Per Tag Line Size (Bytes)EDX Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0CPUID 131