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AMD64 Technology 24594 Rev. 3.10 February 2005RCRRotate Through Carry RightRotates the bits of a register or memory location (first operand) to the right (towardthe less significant bit positions) and through the carry flag by the number of bitpositions in an unsigned immediate value or the CL register (second operand). Thebits rotated through the carry flag are rotated back in at the left end (msb) of the firstoperand location.The processor masks the upper three bits in the count operand, thus restricting thecount to a number between 0 and 31. When the destination is 64 bits wide, theprocessor masks the upper two bits of the count, providing a count in the range of 0 to63.For 1-bit rotates, the instruction sets the OF flag to the exclusive OR of the CF flag(before the rotate) and the most significant bit of the original value. When the rotatecount is greater than 1, the OF flag is undefined. When the rotate count is 0, no flagsare affected.Mnemonic Opcode DescriptionRCR reg/mem8, 1 D0 /3RCR reg/mem8,CL D2 /3RCR reg/mem8,imm8C0 /3 ibRCR reg/mem16,1 D1 /3RCR reg/mem16,CL D3 /3RCR reg/mem16, imm8C1 /3 ibRCR reg/mem32,1 D1 /3Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right 1 bit.Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right the number of bits specified in the CLregister.Rotate the 9 bits consisting of the carry flag and an 8-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.Rotate the 17 bits consisting of the carry flag and a 16-bit registeror memory location right 1 bit.Rotate the17 bits consisting of the carry flag and a 16-bit registeror memory location right the number of bits specified in the CLregister.Rotate the 17 bits consisting of the carry flag and a 16-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.Rotate the 33 bits consisting of the carry flag and a 32-bit registeror memory location right 1 bit.242 RCR
24594 Rev. 3.10 February 2005 AMD64 TechnologyMnemonic Opcode DescriptionRCR reg/mem32,CL D3 /3Rotate 33 bits consisting of the carry flag and a 32-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem32, imm8C1 /3 ibRotate the 33 bits consisting of the carry flag and a 32-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.RCR reg/mem64,1 D1 /3RCR reg/mem64,CL D3 /3Rotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location right 1 bit.Rotate 65 bits consisting of the carry flag and a 64-bit register ormemory location right the number of bits specified in the CLregister.RCR reg/mem64, imm8Related InstructionsRCL, ROR, ROLrFLAGS AffectedC1 /3 ibRotate the 65 bits consisting of the carry flag and a 64-bit registeror memory location right the number of bits specified by an 8-bitimmediate value.ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFMM21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.ExceptionsException RealVirtual8086 Protected Cause of ExceptionStack, #SS X X X A memory address exceeded the stack segment limit or was noncanonical.General protection,#GPX X XA memory address exceeded a data segment limit or was non-canonical.XXThe destination operand was in a non-writable segment.A null data segment was used to reference memory.RCR 243
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