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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 TechnologyIF (temp_RIP>CS.limit)EXCEPTION [#GP]CS.sel = temp_CSCS.base = temp_CS SHL 4RFLAGS.AC,TF,IF,RF clearedRIP = temp_RIPEXITINT_N_PROTECTED:temp_int_n_vector = byte-sized interrupt vector specified in the instruction,zero-extended to 64 bitstemp_idt_desc = READ_IDT (temp_int_n_vector)IF (temp_idt_desc.attr.type = ’taskgate’)TASK_SWITCH // using tss selector in the task gate as the target tssIF (LONG_MODE) // The size of the gate controls the size of the// stack pushes.V=8-byte // Long mode only uses 64-bit gates.ELSIF ((temp_idt_desc.attr.type = ’intgate32’)|| (temp_idt_desc.attr.type = ’trapgate32’))V=4-byte // Legacy mode, using a 32-bit gateELSE // gate is intgate16 or trapgate16V=2-byte // Legacy mode, using a 16-bit gatetemp_RIP = temp_idt_desc.offsetIF (LONG_MODE){// In long mode, we need to read the 2nd half of a// 16-byte interrupt-gate from the IDT, to get the// upper 32 bits of the target RIPtemp_upper = READ_MEM.q [idt:temp_int_n_vector*16+8]}temp_RIP = tempRIP + (temp_upper SHL 32) // concatenate both halves of RIPCS = READ_DESCRIPTOR (temp_idt_desc.segment, intcs_chk)IF (CS.attr.conforming=1)temp_CPL = CPLELSEtemp_CPL = CS.attr.dplIF (CPL=temp_CPL){IF (LONG_MODE)// no privilege-level changeINT 157

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