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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets <strong>and</strong> CPUID Feature Sets (continued)MOVUPSMove Unaligned PackedSingle-PrecisionFloating-PointMOVZX Move with Zero-Extend 3 BasicMUL Multiply Unsigned 3 BasicMULPDMULPSMULSDMULSSNEGMultiply Packed Double-Precision Floating-PointMultiply Packed Single-Precision Floating-PointMultiply Scalar Double-Precision Floating-PointMultiply Scalar Single-Precision Floating-PointTwo's ComplementNegation333333BasicNOP No Operation 3 BasicNOTOne's ComplementNegation3BasicOR Logical OR 3 BasicORPDORPSInstructionMnemonic Description CPLLogical Bitwise ORPacked Double-PrecisionFloating-PointLogical Bitwise ORPacked Single-PrecisionFloating-Point33<strong>General</strong>-<strong>Purpose</strong>OUT Output to Port 3 BasicOUTS Output String 3 BasicOUTSB Output String Byte 3 BasicInstruction Subset<strong>and</strong> CPUID Feature Set(s) 1128-BitMediaSSESSE2SSESSE2SSESSE2SSE64-BitMediax87<strong>System</strong>1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number <strong>and</strong> type of oper<strong>and</strong>s.478 Appendix D: Instruction Subsets <strong>and</strong> CPUID Feature Sets

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