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AMD64 Technology 24594 Rev. 3.10 February 2005execution in 64-bit long mode offers three primary advantages:access to the eight extended, 64-bit general-purpose registers(for a register set consisting of GPR0–GPR15), access to the 64-bit virtual address space, and access to the RIP-relativeaddressing mode.For further information about the general-purpose instructionsand register resources, see:• “General-Purpose Programming” in Volume 1.• “Summary of Registers and Data Types” on page 30.• “Notation” on page 43.• “Instruction Prefixes” on page 3.• Appendix B, “General-Purpose Instructions in 64-Bit Mode.”In particular, see “General Rules for 64-Bit Mode” onpage 413.60
24594 Rev. 3.10 February 2005 AMD64 TechnologyAAAASCII Adjust After AdditionAdjusts the value in the AL register to an unpacked BCD value. Use the AAAinstruction after using the ADD instruction to add two unpacked BCD numbers.If the value in the lower nibble of AL is greater than 9 or the AF flag is set to 1, theinstruction increments the AH register, adds 6 to the AL register, and sets the CF andAF flags to 1. Otherwise, it does not change the AH register and clears the CF and AFflags to 0. In either case, AAA clears bits 7–4 of the AL register, leaving the correctdecimal digit in bits 3–0.This instruction also makes it possible to add ASCII numbers without having to maskoff the upper nibble ‘3’.Using this instruction in 64-bit mode generates an invalid-opcode exception.Mnemonic Opcode DescriptionAAA 37Create an unpacked BCD number.(Invalid in 64-bit mode.)Related InstructionsAAD, AAM, AASrFLAGS AffectedID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CFExceptionsU U U M U M21 20 19 18 17 16 14 13–12 11 10 9 8 7 6 4 2 0Note: Bits 31–22, 15, 5, 3, and 1 are reserved. A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefinedflags are U.VirtualException Real 8086 Protected Cause of ExceptionInvalid opcode, #UD X This instruction was executed in 64-bit mode.AAA 61
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