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AMD64 Technology 24594 Rev. 3.10 February 2005Table C-1.Differences Between Long Mode and Legacy Mode (continued)Type Subject 64-Bit Mode DifferenceApplies ToCompatibilityMode?x86 Modes Real and virtual-8086 modes not supported yesTask Switching Task switching not supported yes64-bit virtual addressesAddressing4-level paging structuresyesPAE must always be enabledCS, DS, ES, SS segment bases are ignoredSegmentationCS, DS, ES, FS, GS, SS segment limits are ignorednoCS, DS, ES, SS Segment prefixes are ignoredAll pushes are 8 bytes16-bit interrupt and trap gates are illegalSystemProgrammingException andInterrupt Handling32-bit interrupt and trap gates are redefined as 64-bitgates and are expanded to 16 bytesSS is set to null on stack switchyesSS:RSP is pushed unconditionallyAll pushes are 8 bytes16-bit call gates are illegalCall Gates32-bit call gate type is redefined as 64-bit call gate and isexpanded to 16 bytes.yesSS is set to null on stack switchSystem-DescriptorRegistersGDT, IDT, LDT, TR base registers expanded to 64 bitsyesSystem-DescriptorTable Entries andPseudo-descriptorsLGDT and LIDT use expanded 10-byte pseudodescriptors.LLDT and LTR use expanded 16-byte table entries.no452 Appendix C: Differences Between Long Mode and Legacy Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyAppendix DInstruction Subsets and CPUID Feature SetsTable D-1 is an alphabetical list of the AMD64 instruction set,including the instructions from all five of the instructionsubsets that make up the entire AMD64 instruction-setarchitecture:• Chapter 3, “General-Purpose Instruction Reference.”• Chapter 4, “System Instruction Reference.”• “128-Bit Media Instruction Reference” in Volume 4.• “64-Bit Media Instruction Reference” in Volume 5.• “x87 Floating-Point Instruction Reference” in Volume 5.Several instructions belong to—and are described in—multipleinstruction subsets. Table D-1 shows the minimum currentprivilege level (CPL) required to execute each instruction andthe instruction subset(s) to which the instruction belongs. Foreach instruction subset, the CPUID feature set(s) that enablesthe instruction is shown.D.1 Instruction SubsetsFigure D-1 on page 454 shows the relationship between the fiveinstruction subsets and the CPUID feature sets. Dashed-linepolygons represent the instruction subsets. Circles representthe major CPUID feature sets that enable various classes ofinstructions. (There are a few additional CPUID feature sets,not shown, each of which apply to only a few instructions.)The overlapping of the 128-bit and 64-bit media instructionsubsets indicates that these subsets share some commonmnemonics. However, these common mnemonics either havedistinct opcodes for each subset or they take operands in boththe MMX and XMM register sets.The horizontal axis of Figure D-1 shows how the subsets andCPUID feature sets have evolved over time.Appendix D: Instruction Subsets and CPUID Feature Sets 453
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