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AMD64 Technology 24594 Rev. 3.10 February 2005Table D-1.Instruction Subsets and CPUID Feature Sets (continued)LOOPZ Loop if Zero 3 BasicLSL Load Segment Limit 3 BasicLSSLoad SS SegmentRegister3LTR Load Task Register 0 BasicMASKMOVDQUMASKMOVQMAXPDMAXPSMAXSDMAXSSMasked Move DoubleQuadword UnalignedMasked MoveQuadwordMaximum PackedDouble-PrecisionFloating-PointMaximum PackedSingle-PrecisionFloating-PointMaximum ScalarDouble-PrecisionFloating-PointMaximum Scalar Single-Precision Floating-Point3333BasicMFENCE Memory Fence 3 SSE2MINPDMINPSMINSDInstructionMnemonic Description CPLMinimum PackedDouble-PrecisionFloating-PointMinimum Packed Single-Precision Floating-PointMinimum Scalar Double-Precision Floating-Point33333General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSE2SSE2SSESSE2SSESSE2SSESSE264-BitMediaSSE,MMXExtensions1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.x87System474 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable D-1.Instruction Subsets and CPUID Feature Sets (continued)MINSSMinimum Scalar Single-Precision Floating-PointMOV Move 3 BasicMOV CRnMOV DRnMOVAPDMOVAPSMOVDMOVDDUPMOVDQ2QMOVDQAMOVDQUMOVHLPSMOVHPDInstructionMnemonic Description CPLMove to/from ControlRegistersMove to/from DebugRegistersMove Aligned PackedDouble-PrecisionFloating-PointMove Aligned PackedSingle-PrecisionFloating-PointMove Doubleword orQuadwordMove Double-Precisionand DupicateMove Quadword toQuadwordMove Aligned DoubleQuadwordMove Unaligned DoubleQuadwordMove Packed Single-Precision Floating-PointHigh to LowMove High PackedDouble-PrecisionFloating-Point300333333333General-PurposeInstruction Subsetand CPUID Feature Set(s) 1128-BitMediaSSESSE2SSEMMX, SSE2 SSE2 MMXSSE3SSE2SSE2SSE2SSESSE264-BitMediaSSE2x87SystemBasicBasic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 475
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