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AMD64 Technology 24594 Rev. 3.10 February 2005logical registers (FPR0–FPR7 physical registers), and aresupported if the following bit is set:- MMX instructions, indicated by EDX bit 23 of CPUIDstandard function 1 and extended function 8000_0001h.• AMD 3DNow! Instructions—Vector floating-pointinstructions that comprise the AMD 3DNow! technology, usethe MMX logical registers (FPR0–FPR7 physical registers),and are supported if the following bit is set:- AMD 3DNow! instructions, indicated by EDX bit 31 ofCPUID extended function 8000_0001h.• AMD Extensions to MMX Instructions—Vector integerinstructions that use the MMX registers and are supported ifthe following bit is set:- AMD extensions to MMX instructions, indicated by EDXbit 22 of CPUID extended function 8000_0001h.• AMD Extensions to 3DNow! Instructions—Vector floatingpointinstructions that use the MMX registers and aresupported if the following bit is set:- AMD extensions to 3DNow! instructions, indicated byEDX bit 30 of CPUID extended function 8000_0001h.• SSE Instructions—Vector integer instructions that use theMMX registers, single-precision vector and scalar floatingpointinstructions that use the XMM registers, plus otherinstructions for data-type conversion, prefetching, cachecontrol, and memory-access ordering. These instructions aresupported if the following bits are set:- SSE, indicated by EDX bit 25 of CPUID standardfunction 1.- FXSAVE and FXRSTOR, indicated by EDX bit 24 ofCPUID standard function 1 and extended function8000_0001h.Several SSE opcodes are also implemented by the AMDExtensions to MMX Instructions.• SSE2 Instructions—Vector and scalar integer and doubleprecisionfloating-point instructions that use the XMMregisters, plus other instructions for data-type conversion,cache control, and memory-access ordering. Theseinstructions are supported if the following bit is set:- SSE2, indicated by EDX bit 26 of CPUID standardfunction 1.456 Appendix D: Instruction Subsets and CPUID Feature Sets
24594 Rev. 3.10 February 2005 AMD64 TechnologySeveral instructions originally implemented as MMXinstructions are extended in the SSE2 instruction set toinclude opcodes that use XMM registers.• SSE3 Instructions—Horizontal addition and subtraction ofpacked single-precision and double-precision floating pointvalues, simultaneous addition and subtraction of packedsingle-precision and double-precision values, move withdupication, and floating-point-to-integer conversion. Theseinstructions are supported if the following bit is set:- SSE3, indicated by ECX bit 0 of CPUID standardfunction 1.• Long-Mode Instructions—Instructions introduced by AMDwith the AMD64 architecture. These instructions aresupported if the following bit is set:- Long mode, indicated by EDX bit 29 of CPUID extendedfunction 8000_0001h.For complete details on the CPUID feature sets listed inTable D-1, see “Processor Feature Identification” in Volume 2.D.3 Instruction ListTable D-1.Instruction Subsets and CPUID Feature SetsInstructionInstruction Subsetand CPUID Feature Set(s) 1Mnemonic Description CPLGeneral-Purpose128-BitMedia64-BitMediax87SystemAAAASCII Adjust AfterAddition3BasicAADASCII Adjust BeforeDivision3BasicAAMASCII Adjust AfterMultiply3BasicAASASCII Adjust AfterSubtraction3BasicADC Add with Carry 3 Basic1. Columns indicate the instruction subsets. Entries indicate the CPUID feature set(s) to which the instruction belongs.2. Mnemonic is used for two different instructions. Assemblers can distinguish them by the number and type of operands.Appendix D: Instruction Subsets and CPUID Feature Sets 457
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