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Volume 3: General-Purpose and System Instructions - Stanford ...

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AMD64 Technology 24594 Rev. 3.10 February 2005INVLPGInvalidate TLB EntryInvalidates the TLB entry that would be used for the 1-byte memory oper<strong>and</strong>.This instruction invalidates the TLB entry, regardless of the G (Global) bit setting inthe associated PDE or PTE entry <strong>and</strong> regardless of the page size (4 Kbytes, 2 Mbytes,or 4 Mbytes). It may invalidate any number of additional TLB entries, in addition tothe targeted entry.INVLPG is a serializing instruction <strong>and</strong> a privileged instruction. The current privilegelevel must be 0 to execute this instruction.See “Page Translation <strong>and</strong> Protection” in <strong>Volume</strong> 2 for more information on pagetranslation.Mnemonic Opcode DescriptionINVLPG mem8 0F 01 /7 Invalidate the TLB entry for the page containing a specified memorylocation.Related <strong>Instructions</strong>MOV CRn (CR3 <strong>and</strong> CR4)rFLAGS AffectedNoneExceptionsException<strong>General</strong> protection,#GPRealVirtual8086 Protected Cause of ExceptionX X CPL was not 0.308 INVLPG

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