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AMD64 Technology 24594 Rev. 3.10 February 2005Table B-3.Reassigned Instructions in 64-Bit ModeMnemonicOpcode(hex)DescriptionARPL 63DEC and INC 40-4FOpcode for MOVSXD instruction in 64-bit mode.In all other modes, this is the Adjust RequestorPrivilege Level instruction opcode.REX prefixes in 64-bit mode. In all other modes,decrement by 1 and increment by 1.Table B-4 lists instructions that are illegal in long mode.Attempted use of these instructions generates an invalidopcodeexception (#UD).Table B-4.Invalid Instructions in Long ModeMnemonicOpcode(hex)DescriptionSYSENTER 0F 34 System CallSYSEXIT 0F 35 System ReturnB.4 Instructions with 64-Bit Default Operand SizeIn 64-bit mode, two groups of instructions default to 64-bitoperand size without the need for a REX prefix:• Near branches —CALL, Jcc, JrCX, JMP, LOOP, and RET.• All instructions, except far branches, that implicitly referencethe RSP—CALL, ENTER, LEAVE, POP, PUSH, and RET(CALL and RET are in both groups of instructions).Table B-5 lists these instructions.446 Appendix B: General-Purpose Instructions in 64-Bit Mode
24594 Rev. 3.10 February 2005 AMD64 TechnologyTable B-5.Instructions Defaulting to 64-Bit Operand SizeMnemonicOpcode(hex)ImplicitlyReferenceRSPDescriptionCALL E8, FF /2 yes Call Procedure NearENTER C8 yes Create Procedure Stack FrameJcc many no Jump Conditional NearJMP E9, EB, FF /4 no Jump NearLEAVE C9 yes Delete Procedure Stack FrameLOOP E2 no LoopLOOPcc E0, E1 no Loop ConditionalPOP reg/mem 8F /0 yes Pop Stack (register or memory)POP reg 58-5F yes Pop Stack (register)POP FS 0F A1 yesPOP GS 0F A9 yesPOPF, POPFD,POPFQ9DyesPUSH imm8 6A yesPUSH imm32 68 yesPUSH reg/mem FF /6 yesPop Stack into FS SegmentRegisterPop Stack into GS SegmentRegisterPop to rFLAGS Word,Doubleword, or QuadwordPush onto Stack (sign-extendedbyte)Push onto Stack (sign-extendeddoubleword)Push onto Stack (register ormemory)PUSH reg 50-57 yes Push onto Stack (register)PUSH FS 0F A0 yesPush FS Segment Register ontoStackAppendix B: General-Purpose Instructions in 64-Bit Mode 447
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