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Volume 3: General-Purpose and System Instructions - Stanford ...

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24594 Rev. 3.10 February 2005 AMD64 Technology64-bit media instructions<strong>Instructions</strong> that use the 64-bit MMX registers. These areprimarily a combination of MMX <strong>and</strong> 3DNow!instruction sets, with some additional instructions from theSSE <strong>and</strong> SSE2 instruction sets.16-bit modeLegacy mode or compatibility mode in which a 16-bitaddress size is active. See legacy mode <strong>and</strong> compatibilitymode.32-bit modeLegacy mode or compatibility mode in which a 32-bitaddress size is active. See legacy mode <strong>and</strong> compatibilitymode.64-bit modeA submode of long mode. In 64-bit mode, the default addresssize is 64 bits <strong>and</strong> new features, such as register extensions,are supported for system <strong>and</strong> application software.#GP(0)Notation indicating a general-protection exception (#GP)with error code of 0.absoluteSaid of a displacement that references the base of a codesegment rather than an instruction pointer. Contrast withrelative.biased exponentThe sum of a floating-point value’s exponent <strong>and</strong> a constantbias for a particular floating-point data type. The bias makesthe range of the biased exponent always positive, whichallows reciprocation without overflow.byteEight bits.clearTo write a bit value of 0. Compare set.Prefacexvii

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