Volume 3: General-Purpose and System Instructions - Stanford ...

24594 Rev. 3.10 February 2005 AMD64 TechnologyRDTSCPRead Time-Stamp Counter and Processor IDLoads the value of the processor’s 64-bit time-stamp counter into registers EDX:EAX,and loads the value of TSC_AUX into ECX. This instruction ignores operand size.The time-stamp counter is contained in a 64-bit model-specific register (MSR). Theprocessor sets the counter to 0 upon reset and increments the counter every clockcycle. INIT does not modify the TSC.The high-order 32 bits are loaded into EDX, and the low-order 32 bits are loaded intothe EAX register.The TSC_AUX value is contained in the low-order 32 bits of the TSC_AUX register(MSR address C000_0103h). This MSR is initialized by privileged software to anymeaningful value, such as a processor ID, that software wants to associate with thereturned TSC value.When the time-stamp disable flag (TSD) in CR4 is set to 1, the RDTSCP instructioncan only be used at privilege level 0. If the TSD flag is 0, this instruction can be used atany privilege level.Unlike the RDTSC instruction, RDTSCP is a serializing instruction.Use the CPUID instruction to verify support for this instruction.Mnemonic Opcode DescriptionRDTSC P 0F 01 F9 Copy the time-stamp counter into EDX:EAX. and theTSC_AUX register into ECX.Related InstructionsRDTSCrFLAGS AffectedNoneRDTSCP 337