13.07.2015 Views

Volume 3: General-Purpose and System Instructions - Stanford ...

Volume 3: General-Purpose and System Instructions - Stanford ...

Volume 3: General-Purpose and System Instructions - Stanford ...

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

24594 Rev. 3.10 February 2005 AMD64 Technologydoubleword oper<strong>and</strong>s are zero-extended to 64 bits, but the highbits of word <strong>and</strong> byte oper<strong>and</strong>s are not modified by operationsin 64-bit mode. The RFLAGS register is 64 bits wide, but thehigh 32 bits are reserved. They can be written with anything butthey read as zeros (RAZ).not modified for 8-bit oper<strong>and</strong>snot modified for 16-bit oper<strong>and</strong>sregisterencodingzero-extendedfor 32-bit oper<strong>and</strong>slow8-bit16-bit 32-bit 64-bit0AH*ALAXEAXRAX3BH*BLBXEBXRBX1CH*CLCXECXRCX2DH*DLDXEDXRDX6SIL**SIESIRSI7DIL**DIEDIRDI5BPL**BPEBPRBP4SPL**SPESPRSP8R8BR8WR8DR89R9BR9WR9DR910R10BR10WR10DR1011R11BR11WR11DR1112R12BR12WR12DR1213R13BR13WR13DR1314R14BR14WR14DR1415R15BR15WR15DR1563 32 31 16 15 8 7 0Figure 2-3.063 32 31 0<strong>General</strong> Registers in 64-Bit ModeRFLAGSRIP513-309.eps* Not addressable whena REX prefix is used.** Only addressable whena REX prefix is used.Chapter 2: Instruction Overview 31

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!