Configuring Hardware and Communication Connections STEP 7.pdf

Configuring the Distributed I/O (DP)
With constant bus cycle time and cycle synchronization, all cycles concerned have
the same cycle time and length. This keeps the process reaction times of equal
length and, because there are no cycle jumps, they are also shorter. This means
that the previously described case in which information transmission can occur in
the first or second cycle, depending on the position of individual cycles, now no
longer applies.
In the previous example, the DP master handles the cyclic master-slave data
exchange with slaves 1 and 2. After this comes the processing of the acyclic
portions for interrupts, bus acceptances or diagnostic services. The DP master
then retains it for a reserve time until the configured constant DP bus cycle time
has expired in order to compensate for possible network disturbances and retrieve
possible message frame repeats. At this point, a new DP cycle starts with the
global frame (GC).
To ensure that consistent status information for the DP inputs can be read at the
start time of a new DP cycle, the read process must be moved up by the specified
time Ti. This time Ti includes the time for signal preparation and conversion at the
electronic submodules and the time for processing at the inputs on the DP slave
backplane bus.
When using a SIMATIC WinAC RTX (as of V3.1) the following applies: After the
input data for all DP slaves have been read by the DP master, the cyclesynchronized
user program is started automatically (OB 6x).
When using a SIMATIC S7-300/400 the following applies: The start of the cyclesynchronized
user program is influenced by a configured "time delay".
The time To ensures that the process reactions for the user program are sent
consistently and in the equal amounts of time to the terminals of the DP I/O
devices. This time To includes the time for the cyclic master-slave data exchange
for all DP slaves, the time for signal preparation and conversion at the electronic
submodules and the time for processing at the outputs on the DP slave backplane
bus.
Configuring Hardware and Communication Connections with STEP 7
A5E00706939-01 3-85