Configuring Hardware and Communication Connections STEP 7.pdf

Configuring the Distributed I/O (DP)
Settings at the DP Master System
To activate the constant bus cycle time at the DP master system:
1. Double-click the DP master system.
2. In the "General" tab, click on the "Properties" button.
3. In the "Properties - PROFIBUS" dialog box, select the "Network Settings" tab.
4. Select the profile allowed (i.e. "DP")
5. Click the "Options" button.
6. In the "Options" dialog box, select the "Constant Bus Cycle Time" tab and
make the following settings:
- Select the "Activate constant bus cycle" check box. This step activates the
constant DP cycle as the basis for maintaining isochrone mode.
- Select the "Times Ti and To same for all slaves" check box.
- For the time being, leave the other parameters in their default settings.
7. Close this dialog box and any other open dialog boxes as well by clicking "OK"
in each case.
Settings at the Modules in the DP Slave
The address space for each module that is involved in isochrone processing must
be assigned to a process image partition. Isochrone read-in and output is can only
be done by means of process image partitions.
1. Double-click the module.
2. Select the "Addresses" tab.
3. In the drop-down list, select the process image partition that you assigned to
the synchronous cycle interrupt OB when you were assigning parameters to
the CPU.
If the addresses for the modules are outside the address range (i.e. for analog
modules), then you can either select lower address that lies within the
prescribed range of process image partition or change the size of the process
image partition so that the address space for the module now lies in the
process image partition. If choose to do the latter, go to the "Cycle/Clock
Memory" tab and change the "Size of the Process Image" parameter. The
value that you set here apples to all process image partitions.
4. To the extent reasonable, keep the "Input delay" parameter for digital input
modules as low as possible. This is because short input delays result in a
shorter Time Ti and thus in shorter overall reaction times. The critical setting
here the longest input delay time for the DP slaves.
Configuring Hardware and Communication Connections with STEP 7
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