Configuring Hardware and Communication Connections STEP 7.pdf

8.1.1 Special Features of Multicomputing
Slot Rules
Bus Connection
Synchronous Operation of Multiple CPUs (Multicomputing)
In multicomputing mode up to four CPUs can be inserted simultaneously in a
central rack in any order.
If you use CPUs that can manage only module start addresses that are divisible by
four (generally CPUs before 10/98), you must follow this rule for all configured
CPUs when you assign the addresses. The rule applies to a case where you are
also using CPUs that permit byte-by-byte assignment of module start addresses in
single-computing operation.
The CPUs are interconnected via the communication bus (corresponds to a
connection via MPI).
Behavior During Startup and Operation
During startup the CPUs in multicomputing operation check automatically whether
they can synchronize. Synchronization is only possible:
• If all (and only) the configured CPUs are inserted and not defective
• If correct configuration data (SDBs) were created and downloaded for all
inserted CPUs.
If one of these prerequisites is not met, the event is entered in the diagnostic
buffer under the ID 0x49A4. You will find explanations of the event IDs in the
reference online help on standard and system functions (SFBs/SFCs).
When the CPUs exit STOP mode, the startup types are compared (COLD
RESTART/WARM RESTART/HOT RESTART). This ensures that all the CPUs in
the programmable controller execute the same type of startup and all CPUs have
the same operating mode.
Configuring Hardware and Communication Connections with STEP 7
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