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Configuring Hardware and Communication Connections STEP 7.pdf

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Settings at the DP Slave (DP Interface Module)<br />

<strong>Configuring</strong> the Distributed I/O (DP)<br />

Isochrone input <strong>and</strong> output modules have to be made known to the DR interface<br />

modules (i.e. IM 151-1 High Feature) as isochrone components. To do so, proceed<br />

as follows:<br />

1. Double-click the icon for the DP slave (i.e. IM 151-1 High Feature).<br />

2. In the "Properties - DP Slave" dialog box, select the "Isochrone Mode" tab <strong>and</strong><br />

make the following settings:<br />

- Select the "Synchronize DP slave to constant bus cycle time for DP<br />

cycle…" check box.<br />

- Select the modules desired for "isochrone operation." Modules that do not<br />

support isochrone mode or for which this option was not selected will not<br />

be included in a calculation of the Ti (read in process values) times <strong>and</strong> the<br />

To (output process values) times.<br />

3. Confirm your entries <strong>and</strong> close the dialog box by clicking "OK".<br />

After this, a message will appear to remind you that the Ti <strong>and</strong> To times in the<br />

configuration of the DP master system are not yet updated.<br />

Updating the Times (Ti, To <strong>and</strong> the lag time)<br />

To update the Ti <strong>and</strong> To times, go to the "Options" dialog box <strong>and</strong> select the<br />

"Constant Bus Cycle Time" tab, as previously described in the section "Settings at<br />

the DP Master System". Then click the "Recalculate" button.<br />

The calculation process will enter a cycle time in the "Constant DP Cycle" field.<br />

This cycle time is one that will ensure adherence to the DP cycle time even in the<br />

case of strong interference (i.e. EMC related disturbances). Under very stable<br />

conditions, this value can be reduced down to the minimum value. The system<br />

requires that new values be changed in terms of the specified interval. For this<br />

reason, use a stepping switch to change this value. A greater DP cycle time may<br />

be necessary to ensure that OB6x has enough calculation time available to it.<br />

During automatic calculation, the values for Ti <strong>and</strong> To are set to their minimum<br />

values. These values can also be changed <strong>and</strong> set within the limits shown. The<br />

maximum values for Ti <strong>and</strong> To can be extended by setting a greater constant DP<br />

cycle time.<br />

To update the lag time between the global control frame <strong>and</strong> the call of the<br />

synchronous cycle interrupt OB, open the properties sheet for the CPU, select the<br />

"Synchronous Cycle Interrupts" tab <strong>and</strong> then click the "Default" button to have the<br />

value recalculated. In some isolated cases, it may be necessary to move up the<br />

start of OB6x. In this case, correct the calculated value manually. The value<br />

entered is understood to be in milliseconds.<br />

<strong>Configuring</strong> <strong>Hardware</strong> <strong>and</strong> <strong>Communication</strong> <strong>Connections</strong> with <strong>STEP</strong> 7<br />

A5E00706939-01 3-89

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