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Configuring Hardware and Communication Connections STEP 7.pdf

Configuring Hardware and Communication Connections STEP 7.pdf

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<strong>Configuring</strong> the Distributed I/O (DP)<br />

3.12.4 Shortening the Process Reaction Time by Overlapping Ti <strong>and</strong> To<br />

If, in your configuration, you select DP slaves that allow overlapping of Ti <strong>and</strong> To,<br />

you can then shorten the DP cycle <strong>and</strong>, with it, the process reaction time even<br />

further.<br />

For example, IM 153-2 (as of 6ES7 153-2BAx1) supports overlapping of Ti <strong>and</strong> To.<br />

This has no influence on the selection process during configuration, since <strong>STEP</strong> 7<br />

automatically determines the times <strong>and</strong>, based on the configuration selected,<br />

calculates the shortest possible DP cycle time.<br />

Please note the following for the configuration:<br />

• In the tab "Constant Bus Cycle Time", deactivate the option "Times Ti <strong>and</strong> To<br />

same for all slaves" <strong>and</strong> set these times for each slave.<br />

• If modules using inputs as well as outputs are to be used in isochrone mode,<br />

then overlapping Ti <strong>and</strong> To times are possible.<br />

Overlapping Processing<br />

The principle governing the overlapping of Ti <strong>and</strong> To functions as follows.<br />

The peripheral input module is already reading the inputs while the peripheral<br />

output module is sending the process reaction from the user program on to the<br />

outputs.<br />

<strong>Configuring</strong> <strong>Hardware</strong> <strong>and</strong> <strong>Communication</strong> <strong>Connections</strong> with <strong>STEP</strong> 7<br />

3-92 A5E00706939-01

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