M16C/62 Group DATASHEET

Serial I/OMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(UART0)RxD0Clock source selectionf1Bit rate generatorInternal (address 03A116)f8f321 / (n0+1)ExternalUART reception1/16Clock synchronous typeReceptioncontrol circuitUART transmission1/16TransmissionClock synchronous typecontrol circuitClock synchronous type(when internal clock is selected)1/2ReceiveclockTransmitclockTransmit/receiveunitTxD0CLK0CTS0 / RTS0CLKpolarityreversingcircuitClock synchronous type(when internal clock is selected)CTS/RTS selectedCTS/RTS disabledVccCTS/RTS disabledCTS/RTS separatedClock synchronous type(when external clock isselected)RTS0CTS0CTS0 from UART1(UART1)RxD1TxD1Clock source selectionf1Bit rate generatorInternal (address 03A916)f8f321 / (n1+1)External1/161/16UART receptionClock synchronous typeUART transmissionClock synchronous typeClock synchronous type(when internal clock is selected)1/2Receptioncontrol circuitTransmissioncontrol circuitReceiveclockTransmitclockTransmit/receiveunitCLK1CTS1 / RTS1/ CTS0 / CLKS1CLKpolarityreversingcircuitClock synchronous type(when internal clock is selected)Clock output pinselect switchClock synchronous type(when external clock isselected)CTS/RTS disabledCTS/RTS separatedVCCCTS/RTS disabledRTS1CTS1(UART2)RxD2RxD polarityreversing circuitClock source selectionf1Bit rate generatorInternal (address 037916)f8f321 / (n2+1)ExternalCTS0UART reception1/16Clock synchronous typeUART transmission1/16Clock synchronous type1/2CTS0 to UART0Clock synchronous type(when internal clock is selected)Receptioncontrol circuitTransmissioncontrol circuitReceiveclockTransmitclockTransmit/receiveunitTxDpolarityreversingcircuitTxD2CLK2CTS2 / RTS2CLKpolarityreversingcircuitClock synchronous type(when internal clock is selected)CTS/RTSselectedCTS/RTS disabledVccCTS/RTS disabledClock synchronous type(when external clock isselected)RTS2CTS2n0 : Values set to UART0 bit rate generator (BRG0)n1 : Values set to UART1 bit rate generator (BRG1)n2 : Values set to UART2 bit rate generator (BRG2)Figure 1.19.1. Block diagram of UARTi (i = 0 to 2)113