M16C/62 Group DATASHEET

Appendix Standard Serial I/O Mode (Flash Memory Version)Mitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERStandard Serial I/O ModeThe standard serial I/O mode serially inputs and outputs the software commands, addresses and datanecessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specificperipheral unit.The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations likerewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard_____serial I/O mode is started by clearing the reset with an “H” level signal at the P50 (CE) pin, an “L” signal at________the P55 (EPM) pin and an “H” level at the CNVss pin. (For the normal microprocessor mode, set CNVss to“L”.)This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, ifthe boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.Figures 1.31.1 and 1.31.2 show the pin connections for the standard serial I/O mode. Serial data I/O usesfour UART1 pins: CLK1, RxD1, TxD1 and RTS1 (BUSY).The CLK1 pin is the transfer clock input pin and it inputs the external transfer clock. The TxD1 pin outputsthe CMOS signal. The RTS1 (BUSY) pin outputs an “L” level when reception setup ends and an “H” levelwhen the reception operation starts. Transmission and reception data is transferred serially in 8-byteblocks.In the standard serial I/O mode, only the user ROM area shown in Figure 1.31.1 can be rewritten, the bootROM area cannot.The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID codedoes not match the content of the flash memory, the command sent from the peripheral unit (programmer)is not accepted.Function Overview (Standard Serial I/O Mode)In the standard serial I/O mode, software commands, addresses and data are input and output betweenthe flash memory and an external device (peripheral unit, etc.) using a 4-wire clock synchronized serial I/O (UART1). In reception, the software commands, addresses and program data are synchronized withthe rise of the transfer clock input to the CLK1 pin and input into the flash memory via the RxD1 pin.In transmission, the read data and status are synchronized with the fall of the transfer clock and output tothe outside from the TxD1 pin.The TxD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.When busy, either during transmission or reception, or while executing an erase operation or program,the RTS1 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS1 (BUSY)pin is “L” level.Also, data in memory and the status register can be read after inputting a software command. It is possibleto check flash memory operating status or whether a program or erase operation ended successfullyor in error by reading the status register.Software commands and the status register are explained here following.255