M16C/62 Group DATASHEET

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERThe operation of saving registers carried out in the interrupt sequence is dependent on whether thecontent of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If thecontent of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of theprogram counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits ata time. Figure 1.14.7 shows the operation of the saving registers.Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointerindicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).(1) Stack pointer (SP) contains even numberAddressStack areaSequence in which orderregisters are saved[SP] – 5 (Odd)[SP] – 4 (Even)[SP] – 3(Odd)[SP] – 2 (Even)[SP] – 1(Odd)[SP] (Even)Program counter (PCL)Program counter (PCM)Flag register (FLGL)Flag register(FLGH)Programcounter (PCH)(2) Saved simultaneously,all 16 bits(1) Saved simultaneously,all 16 bitsFinished saving registersin two operations.(2) Stack pointer (SP) contains odd numberAddressStack areaSequence in which orderregisters are saved[SP] – 5 (Even)[SP] – 4(Odd)Program counter (PCL)(3)[SP] – 3 (Even)[SP] – 2(Odd)Program counter (PCM)Flag register (FLGL)(4)(1)Saved simultaneously,all 8 bits[SP] – 1 (Even)Flag register(FLGH)Programcounter (PCH)(2)[SP](Odd)Finished saving registersin four operations.Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.After registers are saved, the SP content is [SP] minus 4.Figure 1.14.7. Operation of saving registers62