M16C/62 Group DATASHEET

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InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERReturning from an Interrupt RoutineExecuting the REIT instruction at the end of an interrupt routine returns the contents of the flag register(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter(PC), both of which have been saved in the stack area. Then control returns to the program that was beingexecuted before the acceptance of the interrupt request, so that the suspended process resumes.Return the other registers saved by software within the interrupt routine using the POPM or similar instructionbefore executing the REIT instruction.Interrupt PriorityIf there are two or more interrupt requests occurring at a point in time within a single sampling (checkingwhether interrupt requests are made), the interrupt assigned a higher priority is accepted.Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority levelselect bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardwarepriority is accepted.Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),watchdog timer interrupt, etc. are regulated by hardware.Figure 1.14.8 shows the priorities of hardware interrupts.Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branchesinvariably to the interrupt routine._______________Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address matchFigure 1.14.8. Hardware interrupts prioritiesInterrupt resolution circuitWhen two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highestpriority level. Figure 1.14.9 shows the circuit that judges the interrupt priority level.63
InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERPriority level of each interruptINT1Timer B2Level 0 (initial value)HighTimer B0Timer A3Timer A1Timer B4INT3INT2INT0Timer B1Timer A4Timer A2Timer B3Timer B5UART1 receptionUART0 receptionUART2 reception/ACKPriority of peripheral I/O interrupts(if priority levels are same)A-D conversionDMA1Bus collision detectionSerial I/O4/INT5Timer A0UART1 transmissionUART0 transmissionUART2 transmission/NACKKey input interruptDMA0Serial I/O3/INT4Processor interrupt priority level (IPL)LowInterrupt request level judgment outputTo clock generating circuit (Fig.1.13.3)Interrupt enable flag (I flag)Address matchWatchdog timerDBCNMIResetInterruptrequestacceptedFigure 1.14.9. Maskable interrupts priorities (peripheral I/O interrupts)64
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Customer Interface Publication: KCH
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DescriptionMitsubishi microcomputer
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DescriptionMitsubishi microcomputer
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Pin DescriptionMitsubishi microcomp
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MemoryMitsubishi microcomputersM16C
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UART2 Special Mode RegisterMitsubis
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UART2 Special Mode RegisterMitsubis
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UART2 Special Mode Register 2Mitsub
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UART2 Special Mode Register 2Mitsub
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CRCMitsubishi microcomputersM16C /
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Programmable I/O PortMitsubishi mic
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Usage precautionMitsubishi microcom
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Usage precautionMitsubishi microcom
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Operating maximum frequency [MHZ]Op
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Electrical characteristics (Vcc = 5
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Timing (VCC=5V)Mitsubishi microcomp
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Timing (Vcc = 5V)Mitsubishi microco
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IssuancesignatureReceiptMitsubishi
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Functions To Inhibit Rewriting (Fla
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Appendix Standard Serial I/O Mode (
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CNVSSRESETP93/DA0/TB3INP94/DA1/TB4I
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MITSUBISHI SEMICONDUCTORSM16C/62 Gr
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M16C/62 Group DATASHEET

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