M16C/62 Group DATASHEET

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERTime (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for theDIVX instruction (without wait).Time (b) is as shown in Table 1.14.5.Table 1.14.5. Time required for executing the interrupt sequenceInterrupt vector address Stack pointer (SP) value 16-Bit bus, without wait 8-Bit bus, without waitEvenEven18 cycles (Note 1)20 cycles (Note 1)EvenOdd19 cycles (Note 1)20 cycles (Note 1)Odd (Note 2)Even19 cycles (Note 1)20 cycles (Note 1)Odd (Note 2)Odd20 cycles (Note 1)20 cycles (Note 1)________Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidenceinterrupt or of a single-step interrupt.Note 2: Locate an interrupt vector address in an even address, if possible.BCLKAddress busData busR1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18Address0000 Indeterminate SP-2 SP-4 vec vec+2 PCInterruptinformationIndeterminateIndeterminateSP-2contentsSP-4contentsveccontentsvec+2contentsWThe indeterminate segment is dependent on the queue buffer.If the queue buffer is ready to take an instruction, a read cycle occurs.Figure 1.14.5. Time required for executing the interrupt sequenceVariation of IPL when Interrupt Request is AcceptedIf an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shownin Table 1.14.6 is set in the IPL.Table 1.14.6. Relationship between interrupts without interrupt priority levels and IPLInterrupt sources without priority levels_______Watchdog timer, NMIResetOtherValue set in the IPL70Not changed60