M16C/62 Group DATASHEET

Timing (VCC=5V)Mitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERSwitching characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25 o C, CM15 = “1” unlessotherwise specified)VCC = 5VTable 1.26.21. Memory expansion mode and microprocessor mode(with wait, accessing external memory, multiplex bus area selected)SymbolParameterMeasuring conditionStandardMin. Max.Unittd(BCLK-AD) Address output delay time 25 nsth(BCLK-AD) Address output hold time (BCLK standard) 4 nsth(RD-AD) Address output hold time (RD standard) (Note)nsth(WR-AD) Address output hold time (WR standard) (Note)td(BCLK-CS) Chip select output delay time 25 nsth(BCLK-CS) Chip select output hold time (BCLK standard) 4 nsth(RD-CS) Chip select output hold time (RD standard) (Note)nsth(WR-CS) Chip select output hold time (WR standard) (Note) nstd(BCLK-RD) RD signal output delay time 25 nsth(BCLK-RD) RD signal output hold time 0 nstd(BCLK-WR) WR signal output delay time 25 nsth(BCLK-WR) WR signal output hold time 0 nsFigure 1.26.1td(BCLK-DB) Data output delay time (BCLK standard) 40 nsth(BCLK-DB) Data output hold time (BCLK standard) 4 nstd(DB-WR) Data output delay time (WR standard) (Note) nsth(WR-DB) Data output hold time (WR standard) (Note)nstd(BCLK-ALE) ALE signal output delay time (BCLK standard) 25 nsth(BCLK-ALE) ALE signal output hold time (BCLK standard) – 4 nstd(AD-ALE) ALE signal output delay time (Address standard) (Note)nsth(ALE-AD) ALE signal output hold time (Adderss standard) 30 nstd(AD-RD) Post-address RD signal output delay time 0nstd(AD-WR) Post-address WR signal output delay time 0nstdZ(RD-AD) Address output floating start time 8 nsNote: Calculated according to the BCLK frequency as follows:nsth(RD – AD) =10 9f(BCLK) X 2 [ns]th(WR – AD) =10 9f(BCLK) X 2 [ns]th(RD – CS) =10 9f(BCLK) X 2 [ns]th(WR – CS) =10 9f(BCLK) X 2 [ns]td(DB – WR) =10 9 X 3– 40f(BCLK) X 2[ns]th(WR – DB) =10 9f(BCLK) X 2 [ns]10 9td(AD – ALE) = – 25 f(BCLK) X 2 [ns]190