M16C/62 Group DATASHEET

UART2 Special Mode RegisterMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERIn the first place, the control bits related to the I 2 C bus (simplified I 2 C bus) interface are explained.Bit 0 of the UART special mode register (037716) is used as the I 2 C mode selection bit.Setting “1” in the I 2 C mode select bit (bit 0) goes the circuit to achieve the I 2 C bus (simplified I 2 C bus)interface effective.Table 1.19.9 shows the relation between the I 2 C mode select bit and respective control workings.Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.P70 through P72 conforming to the simplified I 2C busP70/TxD2/SDAP71/RxD2/SCLP72/CLK2NoizeFilterNoizeFilterNoizeFilterSelectorTimerFalling edgedetectionSelectorTimerI/OUART2DQTUART2 IICM=0Selector I/OTimerIICM=1delayIICM=0ArbitrationIICM=1Start condition detectionStop condition detectionI/O RQ Data bus(Port P71 output data latch)UART2 Internal clockIICM=1IICM=1IICM=0IICM=0L-synchronousoutput enabling bitExternal clockSR QPort readingCLKTransmissionregisterUART2UART2Reception registerUART2Bus busyDQTDQT9th pulseBus collisiondetectionACKIICM=1IICM=0IICM=1IICM=0NACKIICM=1IICM=0* With IICM set to 1, the port terminal is to be readableeven if 1 is assigned to P71 of the direction register.UART2 transmission/NACK interruptrequestUART2 reception/ACKinterrupt requestDMA1 requestBus collision/start, stopcondition detectioninterrupt requestTo DMA0, DMA1To DMA0Figure 1.19.27. Functional block diagram for I 2 C modeFigure 1.19.27 shows the functional block diagram for I 2 C mode. Setting “1” in the I 2 C mode selection bit(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutputterminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,so the SDA output changes after SCL fully goes to “L”. An attempt to read Port P71 (SCL) results ingetting the terminal’s level regardless of the content of the port direction register. The initial value of SDAtransmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collisiondetection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stopcondition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detectioninterrupt respectively.The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDAterminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interruptrefers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCLterminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by thestart condition detection, and set to “0” by the stop condition detection.141