M16C/62 Group DATASHEET

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERTable 1.16.1. DMAC specificationsItemNo. of channelsTransfer memory spaceMaximum No. of bytes transferredDMA request factors (Note)Channel priorityTransfer unitTransfer address directionTransfer modeSpecification2 (cycle steal method)• From any address in the 1M bytes space to a fixed address• From a fixed address to any address in the 1M bytes space• From a fixed address to a fixed address(Note that DMA-related registers [002016 to 003F16] cannot be accessed)128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)________ ________ ________ ________Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) or both edgeTimer A0 to timer A4 interrupt requestsTimer B0 to timer B5 interrupt requestsUART0 transfer and reception interrupt requestsUART1 transfer and reception interrupt requestsUART2 transfer and reception interrupt requestsSerial I/O3, 4 interrpt requestsA-D conversion interrupt requestsSoftware triggersDMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously8 bits or 16 bitsforward/fixed (forward direction cannot be specified for both source anddestination simultaneously)• Single transfer modeAfter the transfer counter underflows, the DMA enable bit turns to“0”, and the DMAC turns inactive• Repeat transfer modeAfter the transfer counter underflows, the value of the transfer counterreload register is reloaded to the transfer counter.The DMAC remains active unless a “0” is written to the DMA enable bit.DMA interrupt request generation timing When an underflow occurs in the transfer counterActiveWhen the DMA enable bit is set to “1”, the DMAC is active.When the DMAC is active, data transfer starts every time a DMAtransfer request signal occurs.Inactive• When the DMA enable bit is set to “0”, the DMAC is inactive.• After the transfer counter underflows in single transfer modeForward address pointer and At the time of starting data transfer immediately after turning the DMAC active, thereload timing for transfer value of one of source pointer and destination pointer - the one specified for thecounterforward direction - is reloaded to the forward direction address pointer, and the valueof the transfer counter reload register is reloaded to the transfer counter.Writing to registerRegisters specified for forward direction transfer are always write enabled.Registers specified for fixed address transfer are write-enabled whenthe DMA enable bit is “0”.Reading the registerCan be read at any time.However, when the DMA enable bit is “1”, reading the register set up as theforward register is the same as reading the value of the forward address pointer.Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enableflag (I flag) nor by the interrupt priority level.73