M16C/62 Group DATASHEET

Clock asynchronous serial I/O (UART) modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(3) Clock-asynchronous serial I/O mode (used for the SIM interface)The SIM interface is used for connecting the microcomputer with a memory card or the like; adding someextra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table1.19.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).Table 1.19.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)ItemSpecificationTransfer data format • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)• One stop bit (bit 4 of address 037816 = “0”)• With the direct format chosenSet parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)Set data logic to “direct” (bit 6 of address 037D16 = “0”).Set transfer format to LSB (bit 7 of address 037C16 = “0”).• With the inverse format chosenSet parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)Set data logic to “inverse” (bit 6 of address 037D16 = “1”)Set transfer format to MSB (bit 7 of address 037C16 = “1”)Transfer clock• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32(Do not set external clock)Transmission / reception controlOther settings______________• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)• The sleep mode select function is not available for UART2• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)Transmission start condition • To start transmission, the following requirements must be met:- Transmit enable bit (bit 0 of address 037D16) = “1”- Transmit buffer empty flag (bit 1 of address 037D16) = “0”Reception start condition • To start reception, the following requirements must be met:- Reception enable bit (bit 2 of address 037D16) = “1”- Detection of a start bitInterrupt request • When transmittinggeneration timingWhen data transmission from the UART2 transfer register is completed(bit 4 of address 037D16 = “1”)• When receivingWhen data transfer from the UART2 receive register to the UART2 receivebuffer register is completedError detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)• Framing error (see the specifications of clock-asynchronous serial I/O)• Parity error (see the specifications of clock-asynchronous serial I/O)- On the reception side, an “L” level is output from the TXD2 pin by use of the parity errorsignal output function (bit 7 of address 037D16 = “1”) when a parity error is detected- On the transmission side, a parity error is detected by the level of input tothe RXD2 pin when a transmission interrupt occurs• The error sum flag (see the specifications of clock-asynchronous serial I/O)Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note alsothat the UARTi receive interrupt request bit is not set to “1”.136