M16C/62 Group DATASHEET

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(3) The priorities of channels and DMA transfer timingIf a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period fromthe leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrentlyturn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer.When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single busaccess, then DMA1 starts data transfer and gives the bus right to the CPU.An example in which DMA transfer is carried out in minimum cycles at the time when DMA transferrequest signals due to external factors concurrently occur.Figure 1.16.6 An example of DMA transfer effected by external factors.An example in which DMA transmission is carried out in minimumcycles at the time when DMA transmission request signals due toexternal factors concurrently occur.BCLKDMA0DMA1CPUINT0 Obtainment of thebus rightDMA0request bitINT1DMA1request bitFigure 1.16.6. An example of DMA transfer effected by external factors81