M16C/62 Group DATASHEET

Timing (Vcc = 3V)Mitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERVCC = 3VSwitching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25 o C, CM15 = “1” unlessotherwise specified)Table 1.26.40. Memory expansion and microprocessor modes(when accessing external memory area with wait, and select multiplexed bus)SymbolParameterMeasuring conditionStandardMin. Max.Unittd(BCLK-AD) Address output delay time 60 nsth(BCLK-AD) Address output hold time (BCLK standard) 4 nsth(RD-AD) Address output hold time (RD standard) (Note)nsth(WR-AD) Address output hold time (WR standard) (Note)nstd(BCLK-CS) Chip select output delay time 60 nsth(BCLK-CS) Chip select output hold time (BCLK standard) 4 nsth(RD-CS) Chip select output hold time (RD standard) (Note)nsth(WR-CS) Chip select output hold time (WR standard) (Note) nstd(BCLK-RD) RD signal output delay time 60 nsth(BCLK-RD) RD signal output hold time 0 nstd(BCLK-WR) WR signal output delay time Figure 1.26.160 nsth(BCLK-WR) WR signal output hold time 0 nstd(BCLK-DB) Data output delay time (BCLK standard) 80 nsth(BCLK-DB) Data output hold time (BCLK standard) 4 nstd(DB-WR) Data output delay time (WR standard) (Note) nsth(WR-DB) Data output hold time (WR standard) (Note)nstd(BCLK-ALE) ALE signal output delay time (BCLK standard) 60 nsth(BCLK-ALE) ALE signal output hold time (BCLK standard) – 4 nstd(AD-ALE) ALE signal output delay time (Address standard) (Note) nsth(ALE-AD) ALE signal output hold time(Address standard) 50 nstd(AD-RD) Post-address RD signal output delay time 0nstd(AD-WR) Post-address WR signal output delay time 0nstdZ(RD-AD) Address output floating start time 8 nsNote: Calculated according to the BCLK frequency as follows:th(RD – AD) =10 9f(BCLK) X 2 [ns]th(WR – AD) =10 9f(BCLK) X 2 [ns]th(RD – CS) =10 9f(BCLK) X 2 [ns]th(WR – CS) =td(DB – WR) =10 9f(BCLK) X 2 [ns]10 9 X 3– 80f(BCLK) X 2 [ns]th(WR – DB) =10 9f(BCLK) X 2 [ns]10 9td(AD – ALE) = – 45 f(BCLK) X 2 [ns]204