M16C/62 Group DATASHEET

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERInterrupt ControlDescriptions are given here regarding how to enable or disable maskable interrupts and how to set thepriority to be accepted. What is described here does not apply to non-maskable interrupts.Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selectionbit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent isindicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bitare located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and theIPL are located in the flag register (FLG).Figure 1.14.3 shows the memory map of the interrupt control registers.55