M16C/62 Group DATASHEET

UART2 Special Mode Register 2Mitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERP70/TXD2/SDAP71/RXD2/SCLSelectorNoizeFilterNoizeFilterNoizeFilterUART2TimerI/0DQTI/0SelectorUART2IICM=1IICM=1IICM=0IICM=1IICM=0Start condition detectionStop condition detectionFalling edgedetectionIICM=1delayIICM=0SDHIALSL-synchronousoutput enabling bitRArbitrationTransmission registerUART2Data registerInternal clockSWC2External clockRSRReception registerUART2QCLKcontrolBusbusyDQTDQT9th pulseBus collisiondetectionUART2Falling of 9th pulseIICM=0orIICM2=1IICM=1and IICM2=0IICM=0or IICM2=1IICM=1and IICM2=0ACKNACKIICM=1IICM=0To DMA0, DMA1UART2 transmission/NACK interruptrequestTo DMA0UART2 reception/ACK interrupt requestDMA1 requestBus collision/start, stop condition detectioninterrupt requestSSWCP72/CLK2SelectorUART2IICM=0I/0TimerPort reading* With IICM set to 1, the port terminal is to be readableeven if 1 is assigned to P71 of the direction register.Figure 1.19.30. Functional block diagram for I 2 C modeFunctions available in I 2 C mode are shown in Figure 1.19.30 — a functional block diagram.Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Settingthis bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state theinstant when the arbitration loss detection flag is set to "1".Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if thefalling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start countingwithin the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stopscounting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to thisfunction, the UART2 transmission-reception clock becomes the logical product of the signal flowingthrough the internal SCL and that flowing through the SCL pin. This function operates over the periodfrom the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of theninth bit. To use this function, choose the internal clock for the transfer clock.Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to"0" frees the output fixed to "L".146