M16C/62 Group DATASHEET

DMACMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(2) DMAC transfer cyclesAny combination of even or odd transfer read and write addresses is possible. Table 1.16.2 shows thenumber of DMAC transfer cycles.The number of DMAC transfer cycles can be calculated as follows:No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x kTable 1.16.2. No. of DMAC transfer cyclesSingle-chip mode Memory expansion modeTransfer unit Bus width Access address Microprocessor modeNo. of read No. of write No. of read No. of writecycles cycles cycles cycles16-bit Even 1 1 1 18-bit transfers (BYTE= “L”) Odd 1 1 1 1(DMBIT= “1”) 8-bit Even — — 1 1(BYTE = “H”) Odd — — 1 116-bit Even 1 1 1 116-bit transfers (BYTE = “L”) Odd 2 2 2 2(DMBIT= “0”) 8-bit Even — — 2 2(BYTE = “H”) Odd — — 2 2Coefficient j, kInternal memoryExternal memoryInternal ROM/RAM Internal ROM/RAM SFR area Separate bus Separate bus MultiplexNo wait With wait No wait With wait bus1 2 2 1 2 379