M16C/62 Group DATASHEET

Timing (VCC=5V)Mitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERVCC = 5VTiming requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25 o C unless otherwise specified)Table 1.26.6. External clock inputtctw(H)tw(L)trtfSymbolParameterExternal clock input cycle timeExternal clock input HIGH pulse widthExternal clock input LOW pulse widthExternal clock rise timeExternal clock fall timeStandardMin. Max.62.525251515UnitnsnsnsnsnsTable 1.26.7. Memory expansion and microprocessor modesSymbolParametertac1(RD-DB) Data input access time (no wait)tac2(RD-DB) Data input access time (with wait)tac3(RD-DB) Data input access time (when accessing multiplex bus area)tsu(DB-RD) Data input setup timetsu(RDY-BCLK )RDY input setup timetsu(HOLD-BCLK ) HOLD input setup timeth(RD-DB) Data input hold timeth(BCLK -RDY) RDY input hold timeth(BCLK-HOLD )HOLD input hold timetd(BCLK-HLDA ) HLDA output delay timeNote: Calculated according to the BCLK frequency as follows:StandardMin. Max.(Note)(Note)(Note)40304000040Unitnsnsnsnsnsnsnsnsnsns10 9tac1(RD – DB) = – 45f(BCLK) X 2 [ns]3 X 10 9 tac2(RD – DB) = – 45f(BCLK) X 2 [ns]tac3(RD – DB) =3 X 10 9 – 45f(BCLK) X 2[ns]185