M16C/62 Group DATASHEET

Bus ControlMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER________(5) The RDY signal________RDY is a signal that facilitates access to an external device that requires long access time. As shown in________Figure 1.12.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.________If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table1.12.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.12.3 shows an____________example in which the RD signal is prolonged by the RDY signal.________The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the________chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to________all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated asproperly as in non-using.Table 1.12.5. Microcomputer status in ready state (Note)Oscillation___Item_____R/W signal, address bus, data bus, CS__________ALE signal, HLDA, programmable I/O portsStatusOn________Maintain status when RDY signal receivedInternal peripheral circuitsOn________Note: The RDY signal cannot be received immediately prior to a software wait.In an instance of separate busBCLKRDCSi(i=0 to 3)RDYtsu(RDY - BCLK)In an instance of multiplexed busAccept timing of RDY signalBCLKRDCSi(i=0 to 3)RDYtsu(RDY - BCLK): Wait using RDY signal: Wait using software_____Accept timing of RDY signal________Figure 1.12.3. Example of RD signal extended by RDY signal36