M16C/62 Group DATASHEET

UART2 Special Mode RegisterMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERSome other functions added are explained here. Figure 1.19.28 shows their workings.Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. Thebus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformityis detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. Ifthis bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than atthe rising edge of the transfer clock.Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enablebit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the buscollision detect interrupt request bit (nonconformity).Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bitto “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)0: Rising edges of the transfer clockCLKTxD/RxD1: Timer A0 overflowTimer A02. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)CLKTxD/RxDBus collisiondetect interruptrequest bitTransmitenable bit3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)0: In normal stateCLKTxDEnabling transmissionWith "1: falling edge of RxD2" selectedCLKTxDRxDFigure 1.19.28. Some other functions added143