M16C/62 Group DATASHEET

Clock asynchronous serial I/O (UART) modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERTcTransfer clockTransmit enablebit(TE)Transmit bufferempty flag(TI)TxD2RxD2Signal conductor level(Note 2)Transmit registerempty flag (TXEPT)“1”“0”“1”“0”“1”“0”StartbitSTData is set in UART2 transmit buffer registerD0 D1 D2 D3 D4 D5 D6 D7ParitybitPSPStopbitNote 1Transferred from UART2 transmit buffer register to UART2 transmit registerST D0 D1 D2 D3 D4 D5 D6 D7 PA “L” level returns from TxD2 due tothe occurrence of a parity error.ST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPThe level is detected by theinterrupt routine.SPThe level isdetected by theinterrupt routine.Transmit interrupt “1”request bit (IR) “0”Shown in ( ) are bit symbols.The above timing applies to the following settings :• Parity is enabled.• One stop bit.• Transmit interrupt cause select bit = “1”.Cleared to “0” when interrupt request is accepted, or cleared by softwareTc = 16 (n + 1) / fifi : frequency of BRG2 count source (f1, f8, f32)n : value set to BRG2Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.Note 2: Equal in waveform because TxD2 and RxD2 are connected.TcTransfer clockReceive enablebit (RE)“1”“0”StartbitParitybitStopbitRxD2STD0 D1 D2 D3 D4 D5 D6 D7PSPST D0 D1 D2 D3 D4 D5 D6 D7 P SPTxD2Signal conductor level(Note)STD0 D1 D2 D3 D4 D5 D6 D7PSPA “L” level returns from TxD2 due tothe occurrence of a parity error.ST D0 D1 D2 D3 D4 D5 D6 D7 P SPReceive completeflag (RI)“1”“0”Receive interrupt“1”request bit (IR) “0”Read to receive bufferRead to receive bufferShown in ( ) are bit symbols.The above timing applies to the following settings :• Parity is enabled.• One stop bit.• Transmit interrupt cause select bit = “0”.Cleared to “0” when interrupt request is accepted, or cleared by softwareTc = 16 (n + 1) / fifi : frequency of BRG2 count source (f1, f8, f32)n : value set to BRG2Note: Equal in waveform because TxD2 and RxD2 are connected.Figure 1.19.22. Typical transmit/receive timing in UART mode (used for the SIM interface)137