M16C/62 Group DATASHEET

Bus ControlMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(8) BCLK outputThe user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).When set to “1”, the output floating.Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protectregister (address 000A16) to “1”.(9) Software waitA software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting thewait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has beenreset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLKcycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referringto the recommended operating conditions (main clock input oscillation frequency) of the electric character-________istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’sbits 4 to 7 must be set to “0”.When the wait bit of the processor mode register 1 is “0”, software waits can be set independently foreach of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register_______ _______correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed inone BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bitsdefault to “0” after the microcomputer has been reset.The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,insert a software wait if using the multiplex bus to access the external memory area.Table 1.12.8 shows the software wait and bus cycles. Figure 1.12.5 shows example bus timing whenusing software waits.Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protectregister (address 000A16) to “1”.Table 1.12.8. Software waits and bus cyclesArea Bus status Wait bitBits 4 to 7 of chip selectcontrol registerBus cycleSFRInternalROM/RAMInvalid Invalid 2 BCLK cycles0 Invalid 1 BCLK cycle1 Invalid2 BCLK cyclesSeparate bus 0 1 1 BCLK cycleExternalmemoryareaSeparate bus 0 0 2 BCLK cyclesSeparate bus 1 0 (Note) 2 BCLK cyclesMultiplex bus 0 0 3 BCLK cyclesMultiplex bus 1 0 (Note)3 BCLK cyclesNote: When using the RDY signal, always set to “0”.38