M16C/62 Group DATASHEET

Clock synchronous serial I/O modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER• Example of transmit timing (when internal clock is selected)TcTransfer clockTransmit enablebit (TE)Transmit bufferempty flag (Tl)CTSiCLKi“1”“0”“1”“0”“H”“L”Data is set in UARTi transmit buffer registerTransferred from UARTi transmit buffer register to UARTi transmit registerTCLKStopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0”TxDiD0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7Transmit“1”register empty“0”flag (TXEPT)Transmit interrupt “1”request bit (IR) “0”Shown in ( ) are bit symbols.Cleared to “0” when interrupt request is accepted, or cleared by softwareThe above timing applies to the following settings:• Internal clock is selected.• CTS function is selected.• CLK polarity select bit = “0”.• Transmit interrupt cause select bit = “0”.Tc = TCLK = 2(n + 1) / fifi: frequency of BRGi count source (f1, f8, f32)n: value set to BRGi• Example of receive timing (when external clock is selected)Receive enable“1”bit (RE) “0”Transmit enablebit (TE)Transmit bufferempty flag (Tl)RTSiCLKiRxDi“1”“0”“1”“0”“H”“L”Dummy data is set in UARTi transmit buffer registerTransferred from UARTi transmit buffer register to UARTi transmit register1 / fEXTReceive data is taken inD0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5Receive completeflag (Rl)“1”“0”Transferred from UARTi receive registerto UARTi receive buffer registerRead out from UARTi receive buffer registerReceive interrupt “1”request bit (IR) “0”Shown in ( ) are bit symbols.Cleared to “0” when interrupt request is accepted, or cleared by softwareThe above timing applies to the following settings:• External clock is selected.• RTS function is selected.• CLK polarity select bit = “0”.fEXT: frequency of external clockMeet the following conditions are met when the CLKinput before data reception = “H”• Transmit enable bit “1”• Receive enable bit “1”• Dummy data write to UARTi transmit buffer registerFigure 1.19.10. Typical transmit/receive timings in clock synchronous serial I/O mode125