M16C/62 Group DATASHEET

Watchdog TimerMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERWatchdog TimerThe watchdog timer has the function of detecting when the program is out of control. The watchdog timer isa 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdogtimer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for theBCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculatedas given below. The watchdog timer's period is, however, subject to an error due to the prescaler.With XIN chosen for BCLKWatchdog timer period =prescaler dividing ratio (16 or 128) X watchdog timer count (32768)BCLKWith XCIN chosen for BCLKWatchdog timer period =prescaler dividing ratio (2) X watchdog timer count (32768)BCLKFor example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of theprescaler, then the watchdog timer's period becomes approximately 32.8 ms.The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and whena watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer isreset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started bywriting to the watchdog timer start register (address 000E16).Figure 1.15.1 shows the block diagram of the watchdog timer. Figure 1.15.2 shows the watchdog timerrelatedregisters.Prescaler1/16“CM07 = 0”“WDC7 = 0”BCLKHOLD1/128“CM07 = 0”“WDC7 = 1”Watchdog timerWatchdog timerinterrupt request1/2“CM07 = 1”Write to the watchdog timerstart register(address 000E16)Set to“7FFF16”RESETFigure 1.15.1. Block diagram of watchdog timer70