M16C/62 Group DATASHEET

InterruptMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTERInterrupt control register (Note2) b7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetTBiIC(i=3 to 5) 004516 to 004716 XXXXX0002BCNIC 004A16 XXXXX0002DMiIC(i=0, 1) 004B16, 004C16 XXXXX0002KUPIC 004D16 XXXXX0002ADIC 004E16 XXXXX0002SiTIC(i=0 to 2) 005116, 005316, 004F16 XXXXX0002SiRIC(i=0 to 2) 005216, 005416, 005016 XXXXX0002TAiIC(i=0 to 4) 005516 to 005916 XXXXX0002TBiIC(i=0 to 2) 005A16 to 005C16 XXXXX0002Bit symbolILVL0ILVL1ILVL2IRBit nameInterrupt priority levelselect bitInterrupt request bitb2 b1 b0Function0 0 0 : Level 0 (interrupt disabled)0 0 1 : Level 10 1 0 : Level 20 1 1 : Level 31 0 0 : Level 41 0 1 : Level 51 1 0 : Level 61 1 1 : Level 70 : Interrupt not requested1 : Interrupt requestedNothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turnsout to be indeterminate.RW (Note 1)Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).Note 2: To rewrite the interrupt control register, do so at a point that dose not generate theinterrupt request for that register. For details, see the precautions for interrupts.0b7 b6 b5 b4 b3 b2 b1 b0Symbol Address When resetINTiIC(i=3) 004416 XX00X0002SiIC/INTjIC (i=4, 3) 004816, 004916 XX00X0002(j=5, 4) 004816, 004916 XX00X0002INTiIC(i=0 to 2) 005D16 to 005F16 XX00X0002Bit symbolILVL0ILVL1ILVL2IRBit nameInterrupt priority levelselect bitInterrupt request bitFunctionb2 b1 b00 0 0 : Level 0 (interrupt disabled)0 0 1 : Level 10 1 0 : Level 20 1 1 : Level 31 0 0 : Level 41 0 1 : Level 51 1 0 : Level 61 1 1 : Level 70: Interrupt not requested1: Interrupt requestedRW(Note 1)POLReserved bitPolarity select bit0 : Selects falling edge1 : Selects rising edgeAlways set to “0”Nothing is assigned.In an attempt to write to these bits, write “0”. The value, if read, turnsout to be indeterminate.Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).Note 2: To rewrite the interrupt control register, do so at a point that dose not generate theinterrupt request for that register. For details, see the precautions for interrupts.Figure 1.14.3. Interrupt control registers56