M16C/62 Group DATASHEET

Clock synchronous serial I/O modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(c) Transfer clock output from multiple pins function (UART1)This function allows the setting two transfer clock output pins and choosing one of the two to output aclock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.19.13.)The multiple pins function is valid only when the internal clock is selected for UART1. Note that when_______ _______this function is selected, UART1 CTS/RTS function cannot be used.MicrocomputerTXD1 (P67)CLKS1 (P64)CLK1 (P65)INCLKINCLKNote: This applies when the internal clock is selected and transmissionis performed only in clock synchronous serial I/O mode.Figure 1.19.13. The transfer clock output from the multiple pins function usage(d) Continuous receive modeIf the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) isset to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer registeris read out, the unit simultaneously goes to a receive enable state without having to set dummy data tothe transmit buffer register back again._______ _______(e) Separate CTS/RTS pins function (UART0)This function works the same way as in the clock asynchronous serial I/O (UART) mode. The methodof setting and the input/output pin functions are both the same, so refer to select function in the nextsection, “(2) Clock asynchronous serial I/O (UART) mode”. Note that this function is invalid if thetransfer clock output from the multiple pins function is selected.(f) Serial data logic switch function (UART2)When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register orreading from receive buffer register, data is reversed. Figure 1.19.14 shows the example of serial datalogic switch timing.•When LSB firstTransfer clock“H”“L”TxD2(no reverse)TxD2(reverse)“H”“L”“H”“L”D0 D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7Figure 1.19.14. Serial data logic switch timing127