M16C/62 Group DATASHEET

Clock asynchronous serial I/O (UART) modeMitsubishi microcomputersM16C / 62 GroupSINGLE-CHIP 16-BIT CMOS MICROCOMPUTER(c) Function for switching serial data logic (UART2)When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to thetransmission buffer register or reading the reception buffer register. Figure 1.19.20 shows the exampleof timing for switching serial data logic.• When LSB first, parity enabled, one stop bitTransfer clock“H”“L”TxD2(no reverse)“H”“L”STD0 D1 D2 D3 D4 D5 D6 D7 P SPTxD2(reverse)“H”“L”ST D0 D1 D2 D3 D4 D5 D6 D7 PSPST : Start bitP : Even paritySP : Stop bitFigure 1.19.20. Timing for switching serial data logic(d) TxD, RxD I/O polarity reverse function (UART2)This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) forusual use.(e) Bus collision detection function (UART2)This function is to sample the output level of the TXD pin and the input level of the RXD pin at the risingedge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.19.21shows the example of detection timing of a buss collision (in UART mode).Transfer clock“H”“L”TxD2“H”“L”STSPRxD2“H”“L”STSPBus collision detectioninterrupt request signal“1”“0”Bus collision detectioninterrupt request bit“1”“0”ST : Start bitSP : Stop bitFigure 1.19.21. Detection timing of a bus collision (in UART mode)135