Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyThermal Design ofFully-Isolated Bipolar TransistorsS. Russo 1,2 , L. La Spina 1 , V. d’Alessandro 2 , N. Rinaldi 2 , and L. K. Nanver 11Laboratory of Electronic Components, Technology, and Materials (ECTM), DIMES,Delft University of Technology, Feldmannweg 17, Delft 2628 CT, The Netherlands.2Department of Electronics and Telecommunications Engineering,University of Naples ‘‘Federico II,’’ via Claudio 21, 80125 Naples, Italy.E-mail: salvatore.russo3@unina.it. Phone: +39-081-7683145. Fax: +39-081-5934448.Abstract - The impact of layout parameters on the thermalbehavior of BJTs with full dielectric isolation is extensivelyanalyzed by measurements and numerical simulations. Theinfluence of the aspect ratio of the emitter stripe as well as theconsequences of the device scaling are investigated from athermal viewpoint. It is shown that the metallization designplays a key role in the thermal response of fully-isolateddevices. As a conclusion, plain guidelines are provided tooptimize the thermal design.I. INTRODUCTIONThe continuous trends in miniaturization, deviceintegration, and performance demands in the semiconductorindustry are all elements that constantly push researchtoward more severe isolation schemes. Particularly, the useof silicon-on-insulator substrates and trench isolationproduces clear improvements in terms of reduced parasiticsand minimization of crosstalk via the substrate, thuscontributing to increased speed of RF devices and circuits.On the other hand, the poor thermal conductivity of mostmaterials used to electrically insulate the devices enhancesthe thermal issues that could impose a limit on the currentdensity of high-speed transistors in the close future [1].Only a few papers have been published that analyze thethermal behavior of fully-isolated bipolar junction transistors(BJTs) fabricated on conventional silicon substrates [2]-[4].In all these works, the structure under analysis is comprisedof an “island” (also referred to as “tub” or “box”) surroundedby insulating trench and buried oxide, and embedded in asilicon substrate. In particular, in [2] it is suggested toestimate the overall thermal resistance by considering acombination of individual thermal resistances associatedwith the heat paths. In [3], an effort is made to analyticallydescribe the thermal response of vertical BJTs with the aidof measurements and numerical simulations. In [4], aparametric analysis of the thermal behavior under steadystateconditions is carried out through an analytical modelsupported by a finite-element-method (FEM) analysis.However, none of these investigations covers the case ofsilicon BJTs fabricated in silicon-on-glass (SOG) technology[5], where the low heat-transfer capability of the glasssubstrate, as well as of all other materials surrounding thesilicon island, significantly affects the nature of the heatpropagation. Although the analysis of the thermal behaviorof SOG BJTs has been the subject of various works (e.g.,[6]-[8]), to date no attempts have been made to clarify theimpact of layout parameters upon the thermal resistance ofsuch devices. This contribution is aimed at supplying designguidelines through an extensive experimental analysis ofSOG test structures. The study is supported by detailed fully3-D numerical simulations [9].II.EXPERIMENTAL MATERIALA. Test structuresAll the experiments are conducted on bipolar junctiontransistors fabricated in SOG technology within a 0.94-μmthicksilicon island. In order to study the influence of all thegeometrical parameters, several structures with differentlayouts (i.e., different areas and aspect ratios of the emitterstripe, and distances between emitter stripe and trench) areanalyzed: a schematic illustration of the top-view of thedevices, with the nomenclature used throughout thismanuscript, is depicted in Fig. 1, and a description of thedevices under test is given in Table I.The measurements are performed on a Cascade probingstation equipped with a thermo-chuck and the electricalsignals are handled with an Agilent 4156C parameteranalyzer. The base-emitter junction voltage V BE as a functionof the temperature was calibrated on the basis ofexperimental data measured on bulk-silicon transistors(electrically coinciding with the SOG ones) at variousthermo-chuck temperatures under isothermal (pulsed)conditions.©EDA Publishing/THERMINIC 2008 101ISBN: 978-2-35500-008-9