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III. HEDORIS SIMULATIONSThermal simulations of various device configurationsconfirm the system usability. The set of device thermalsimulations defined by the configuration presented above(Fig.4) is presented on Fig.7. The temperature distribution ofthe bottom (Fig.7a), middle (Fig.7b), and top wafer (Fig.7c)is presented. As the ambient and support temperature is setto the level of 310K, the bottom device wafer is thermallybound to the support temperature. Gaps between wafers arefilled with air. According to the Fig.3 all wafers arethermally and mechanically connected by 33 via/wafer 33through chip via/wafer instances. The Hedoris output post-24-26 September 2008, Rome, Italyto the n’th layer of the device. Assuming the n’th layer to be simulation data shows the local inner-wafer heat-flow.the 1’st wafer, the adjacent n’th+1 layer would be the gap The most important advancement of the Hedoris system isbetween 1’st and 2’nd wafers, filled with air and 33 via that the simulation can be run within Cadence embeddedinstances. Then the n’th+1 layer could model some solid, Spectre universal simulator.liquid or gas filling the gap.aFig.6. The equivalent thermal structure of the BDE elementApart from the ambient and substrate temperature,standalone heat source elements (HS) are defined inconfiguration file by HeatSource statement (Fig.4). Heatsources impose Dirichlet, Neuman or Cauchy boundarythermal conditions to the structure. Heat sources applyparticular temperature (K) or define a power dissipationlevel (mW) for the selected area of the device or any of itscomponents.For transient simulation purposes instances of virtual areaof interest (AOI) can be defined in initial configuration fileby the statement AreaOfInterest (Fig.4). The AOI instancesmake it possible to find the final transient temperaturedistribution in particular regions of the device and tovisualize the time dependent local variation of temperature.Referring to the initial configuration of the device, spatialcoordinates of the layer/device (x, y), the layer/device extent(dx, dy, dz), type of the shape (circle, rectangle, polygon)and the layer/wafer consecutive number have to be specifiedas layer parameters. To define heat source parameters, theinitial configuration file also describe the HS-typedependent: temperature or power dissipation levels. Thedeclaration of the area of interest (AOI) is similar: first fourparameters define spatial coordinates and extent of the AOI(refer to the HS statement). Remaining parameters are theAOI shape and wafer number the particular AOI belongs to.The last parameter is optional. The AOI consecutive numbercan be automatically assigned. If specified manually, theAOI consecutive number is verified and (if necessary)automatically corrected by Hedoris system.Fig.7. Results of thermal simulation for the structure shown onthe Fig.3 for double 40mW heat-flow source.The same can be done in any other multidomain HDLsimulator.IV. COVENTOR SIMULATIONSFinite element modeling and simulation method (FEM) isan alternative to the high level modeling method presented inthe previous paragraph. One of the FEM methoddisadvantages is a need of commercial software dedicated tosupport a particular type of simulation. One of importantFEM-based software advantages is that it is possible to ispossible to create a physical model of almost any real siliconstructure or nanostructure. CoventorWare [7] system is agood example here. It supports defining new materials, realtechnological process list and mask sets. The systemsupports creation of a structure realistic model. ITE usesCoventor-Ware package for FEM based modeling andsimulation. Coupling between thermal, electrical andbc©EDA Publishing/THERMINIC 2008 82ISBN: 978-2-35500-008-9