Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyBlock-Level Thermal Model for Floorplan Stage inVLSI Design FlowShun-Hua Lin Jin-Tai Yan Herming ChiuehDepartment of Communications Department of Computer Science and Department of CommunicationsEngineering Information Engineering EngineeringNational Chiao Tung University Chung-Hua University National Chiao Tung UniversityHsinchu, Taiwan Hsinchu, Taiwan, R.O.C Hsinchu, Taiwanshlin@soclab.org yan@chu.edu.tw chiueh@ieee.orgAbstract-Thermal issues have become a determinant factor toresult in very large scale integrated (VLSI) circuits work ormalfunction. For this reason, the paper proposed an efficientblock-level thermal model for temperature calculation in thefloorplan stage among the integrated circuit (IC) design flow.Furthermore, the model accurately profiles the temperaturedifference between all thermal blocks and overcomes the verylong computational time issue existing in traditional tile-basedthermal model. We not only prove the timing complexity bytheory but also use five floorplan benchmarks to test our model.Observing the experimental results, the temperature calculationtimes for all benchmarks are really direct ratio of total amountof blocks. Hence our block-level thermal model really canreduce the temperature calculating time and provide usefultemperature differences for rearranging the floorplan.I. INTRODUCTIONThe process technology enters nano-meter scale so thesame two-dimensional (2D) IC area can be contained moretransistors than previous process technology. The hightransistor density relatively denotes high power density andhigh operating temperature. High power density and highoperating temperature do not appropriately solve when thethermal arrives a threshold capacity that results in the ICsbroken down. In general, the simplest approach is that addingcooler surrounding the 2D IC but it is not efficient. When theIC manufacturing technology translates from traditional 2DIC into three-dimensional (3D) stack IC, the thermal issuesbecome more serious and more urgent. Hence manyresearchers think how to improve the thermal issues betweenthe 3D stack IC design flows. Now there are many researches[2-5] have focused on and use many methodologies toovercome. Although there are many different approaches tosolve the thermal issues but all of them are formulated theproblem into temperature calculation problem. Because thetemperature degree can obviously differentiate the thermalamount inside every object and easily identify. The first stageis to define the thermal model that can accurately evaluate thetemperature degree. According to the temperature degree, theoriginal floorplans are modified [3][6] or inserted additionalthermal via [4][5][8]. The final goals are to reduce thetemperature degree and solve the thermal issues.According to the above description, the thermal model fortemperature calculation is the key play for solving thermalissues in 2D IC and 3D stack IC. Hence how to define andconstruct the efficient and accurate thermal model is verycrucial. The thermal model defined in [2-8] are namedtile-based thermal model because the floorplan is partitionedinto many tiles. The tile denotes the basic calculating unit.Hence the computation time is excessive and inefficient fortile-based model. When the IC becomes more and morecomplexity, the issue will be more and more serious. In thispaper, an efficient thermal model named block-level thermalmodel is announced. The main goal is to improve and speedup the temperature computational time.The organization of the paper is as follows. The tile-basedthermal model is represented in Section II. The problemformulation is shown in Section III. In Section IV isrepresented block-level thermal model. The experimentalresults and conclusions are respectively shown in Section VIand Section VII. Finally, the acknowledgement is described.II.TILE-BASED THERMAL MODELA. Thermal Modeling in Tile-Based PartitionThe original heat diffusion equation from the energyconservation can be represented as following equationreferenced [1]∂T( x,y,z,t)ρcp = ∇[ k( x,y,z,t) ∇T( x,y,z,t)] + p( x,y,z,t)∂t(1)The thermal boundary condition is as follows:∂T( x,y,z,t)k( x, y,z,t)+ hT i( x,y,z,t) = fi( x,y,z)∂ni(2)T x y,z,tC p x, y,z,t is the,where ( , ) is the temperature ( ° ), ( )3power density of the heat sources ( W / m ), k ( x y,z,t)thermal conductivity ( W m°C)3Kg / m c is the specific heat ( J ( Kg°C))material ( ), is the/ , ρ is the density of the, p/ , h i isthe heat transfer coefficient of the packaging components2( W / m ° C), f i ( x, y,z)is an arbitrary function, and n i is theoutward direction normal to the surface i .Basically, the above equation (1) is nonlinear due to thek x, y,z,t on temperature. As thenonlinear dependence of ( )thermal steady state is reached, the chip temperature does notfollow the instantaneous power dissipation, but insteadremains virtually constant. For full-chip thermal analysis, thesteady state case is only concerned but not transient analysis.©EDA Publishing/THERMINIC 2008 58ISBN: 978-2-35500-008-9