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every thermal block. When the final floorplan has beenexported, the more accurate thermal model like tile-basedthermal model can be used to calculate. In the intermediatesteps, the efficient block-level thermal model can be used tosave temperature calculation time. In conclusion, ourblock-level thermal model is an efficient model fortemperature calculation for floorplan stage in VLSI designflow.TABLE ICases Comparison between block-level floorplan and tile-based floorplanTest Case Case1 Complexity Case2 Complexity# Tiles 5 125 18 5832# Blocks 25 15625 130 2197000Speedup 125 37724-26 September 2008, Rome, Italytotal amount of thermal blocks. In conclusion, the executingtime will be very terrible when the gap continuously growsup.VI. EXPERIMENTAL RESULTSThe block-level thermal model in the paper wasimplemented in C++. The experimental environment isCeleron(R) M Processor 1.5GHz and 1 GB RAM and usedACKNOWLEDGMENTfive floorplan benchmarks including atpe, xerox, hp, ami33,and ami49. The ambient temperature is 25 ° C and power6 2 6 2density is between10 W / m ~ 7 × 10 W / m . In the TABLEII, the experimental results for apte, xerox, ,hp, ami33, andREFERENCESami49 benchmarks are shown. “Benchmark” denotes thenames for the floorplan benchmarks, “Blocks” is total amountof blocks (functional + space blocks) for every benchmark,“Area” is the floorplan region area, “PTemp” is the highesttemperature, “LTemp” is the lowest temperature, “DTemp” isthe difference between the highest and lowest temperature,“Timing” denotes the execution time for all benchmarks tocalculate temperature, “Tile” is the total amount of tiles, and“Tiles/Blocks” is the values for Tiles/Blocks.Exception hp, execution time for all benchmarks is grownwhen block increasing. Because the adjacent relation for hp issimpler than others, the thermal conductivity matrix can bereduced much computational time. The peak temperature ismainly affected by the power value of every thermal blockbecause the power is power_density × thermal_block_volume.The volume for every thermal block in different benchmarkshas great gap therefore the exported peak temperature is alsovery different. Our purpose is to highlight the temperaturedifferences for the same benchmark.When let tile size is 30× 30 referenced [8], the fivebenchmarks can be partitioned into tile-based floorplan. Thevalues of “Tiles/Blocks” are very large as shown in TABLE II.When the floorplan area and design complexity grow up, thegap will rapidly grow. Although the executing time does notbe cubic growing, the computational time has direct ratio withTABLE IIExperimental Results for apt, xerox, hp, ami33m and ami492VII.CONCLUSIONSIn this paper, the proposed block-level thermal model fortemperature calculation really can save computational time.The executing time is grown up with the total amount ofblocks in our model and the computational complexity fortile-based thermal model also has direct ratio with totalamount of tiles. When the gap between total amount of blocksand tiles rapidly grows up, the temperature calculation time ofour model is more efficient than tile-based thermal model inthe floorplan stage. Meanwhile, block-level thermal modelprovides the useful temperature difference between everythermal block. In conclusion, our block-level thermal modelcan be used to save the temperature calculating time infloorplan stage and shorten the VLSI design flow.This research is supported by National Science Council,Taiwan. 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Wong, “Optimal Redistribution ofWhite Space for Wire Length Minimization,” Asia and SouthPacific Design Automation Conference, pp. 412-417, 2005[7] Eric Wong and Sung Kyu Lim, “Decoupling-Capacitor Planningand Sizing for Noise and Leakage Reduction,” IEEE Trans. onComputer-Aided Design of Integrated Circuits and Systems, pp.2023-2034, 2007[8] Xin Li, Yuchu Ma, Xianlong Hong, Sheqin Dong, and Jason Cong,“LB Based White Space Redistribution for Thermal Via Planningand Performance Optimization in 3D ICs,” Asia and South PacificDesign Automation Conference, pp. 209-211, 2008Benchmark Blocks (FB+SB) Area ( μ m ) PTemp( ° C ) LTemp ( ° C ) DTemp ( ° C ) Time ( sec ond ) Tiles Tiles/BlocksApte 9+3 = 12 9478*12644 31.0181 26.2414 4.7767 0.00023 316*422=133352 1.11E+04xerox 10+9 = 19 3864*5264 78.1498 45.6418 32.508 0.00074 129*176=22704 1.19E+03Hp 11+7 = 18 4116*2450 79.2265 47.6251 31.6014 0.00006 138*82=11316 6.29E+02ami33 33+19 = 52 1134*1064 27.2627 25.6062 1.6565 0.00109 38*36=1368 2.63E+01ami49 49+45 = 94 5670*5152 45.5638 29.6804 15.8834 0.00604 189*172=32508 3.46E+02©EDA Publishing/THERMINIC 2008 63ISBN: 978-2-35500-008-9