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V IN =V DD /2Fig. 5. Short circuit currentV SG =V DD /2I SCV GS =V DD /2For an inverter, power consumption due to short-circuitcurrent scales roughly linearly with input transition time.Slower input transitions create a larger short-circuit windowwhere both transistors are turned on, so more power isconsumed. In an FPGAs programmable routing fabric, thetransition time at the input to each buffer depends strongly ondevice configuration and physical wire parameters.Interconnect wires have significant distributed resistance andcapacitance. As a transition propagates along a net, its edgerate is degraded by resistor capacitor (RC) filtering.Multiplexers listening to the wire add load capacitance alongits length and worsen this effect, as shown in Fig. 6.Fig. 6. Effect of load capacitance on edge rateDetermining accurate transition times at buffer inputsrequires a detailed analysis of each wire. Physical wireparameters and loading effects must be considered. Atransistor-level simulation engine is necessary.E. I/O Power ModelsThe I/O power model is another simulation-based powermodel. A sophisticated model does not simply model each I/Opin as having a capacitive load. Instead, it takes into accountevery possible parameter describing the off-chip board traceat each I/O pin, including relevant termination networks andtransmission line effects, as shown in Fig. 7.Fig. 7. Advanced I/O power board trace model [1]The entire board trace model is should be simulated using aSPICE-like simulator. Consequently the simulation time canbe quite long in time depending on available computingcapacity.24-26 September 2008, Rome, ItalyF. Empirical Dynamic ModelsEmpirical dynamic power models are based entirely onmeasured data. These models are used for blocks, such asembedded SRAM memories and embedded multipliers thatare too large to simulate in a reasonable amount of time, buthave a small enough set of supported configurations that aparameterized measured model will need.The best way to accurately measure the power of a singleblock in a specific configuration in the FPGA is to configurethe FPGA with all instances of a block measured in theconfiguration state under analysis. All other logic andfunctional blocks are configured for the lower poweroperating mode and are not stimulated. Then, specificstimulus patterns are run through all instances of the blockbeing measured to generate the power profile. The resultingpower consumed by the chip is largely the result of the largenumber of blocks under test, and the excess power can besubtracted from the total power. The resulting power, dividedby the number of blocks configured, gives an accurate viewof power for that mode of that block.IV. GLITCHING MINIMIZATION TECHNIQUESSeveral methods have been published for minimizingunnecessary switching activity in the design.Clock-gating techniques have been shown to be veryeffective in the reduction of the switching activity. Thesemethods based on finite state machine (FSM) decomposition.Two sub-FSMs have been computed that together have thesame functionality as the original FSM. For all the transitionswithin one sub-FSM, the clock for the other sub-FSM isdisabled. This way there will be a small amount of logic thatis active most of the time, during which is disabling a muchlarger circuit, the other sub-FSM [2].Other transformation technique for reducing the powerconsumed by functional units called loop-folding. It isdecreasing the switching activity in a data path dominatedcircuit containing loops. The transformation can be integratedinto a high level synthesis [3].The total number of glitches can be reduced by replacingsome existing gates with functionally equivalent ones that canbe “frozen” by asserting a control signal. A frozen gatecannot propagate glitches to its output. An important featureof this method is that it can be applied in place directly tolayout-level descriptions; therefore, it guarantees verypredictable results and minimizes the impact of thetransformation on circuit size and speed [4]. As aconsequence it cannot be used at FPGA designs.Other technique is presented for estimating switchingactivity and power consumption in register-transfer level(RTL). For data path blocks that operate on word-level data, apiecewise linear model has been constructed that capture thevariation of output glitching activity and power consumptionwith various word-level parameters like mean, standarddeviation, spatial and temporal correlations, and glitchingactivity at the block's inputs. For RTL blocks that operate ondata that need not have an associated word-level value, anaccurate bit-level modeling technique is presented forglitching activity as well as power consumption. [5] Thisperforms accurate power estimation for control-flow intensive©EDA Publishing/THERMINIC 2008 150ISBN: 978-2-35500-008-9