Online proceedings - EDA Publishing Association

24-26 September 2008, Rome, ItalyHot-Carrier Effects on Power RF LDMOSDevice ReliabilityM.A. Belaïd a * and K. Ketata ba ISSIG, University of Gabes, 6072 Zrig Gabes, Tunisiab GPM-UMR CNRS 6634, University of Rouen, 76801 Saint Etienne du Rouvray, FranceAbstract-This paper reports comparative reliability of the hotcarrier induced electrical performance degradation in powerRF LDMOS transistors after novel methods for acceleratedageing tests under various conditions (electrical and/or thermalstress). It is important to understand the effects of thereliability degradation mechanisms on the S-parameters and inturn on static and dynamic parameters. The analysis of theexperimental results is presented and the physical processesresponsible for the observed degradation at different stressconditions are studied by means of 2D ATLAS-SILVACOsimulations. The RF performance degradation of hot-carriereffects power RF LDMOS transistors can be explained by thetransconductance and miller capacitance shifts, which areresulted from the interface state generation and trappedelectrons, thereafter results in a build up of negative charge atSi/SiO 2 interface.I. INTRODUCTIONTemperature is a critical parameter, particularly in RFpower electronic devices. This element has a considerableinfluence on reliability and performances [1,2], can limit thelifetime of semiconductors and consequently plays anessential part in failure mechanisms [1]. For these reasonsthermal shocks and cycling conditions are becomingimportant for RF LDMOS in many applications.Hot carrier induced electrical device parameterdegradation in one of the major concerns in devicereliability. The electric parameters of MOS transistor aremore and more sensitive to defects bound, to the presence ofcharges in the gate oxide and at the Si/SiO 2 interface [3,4].The miniaturisation of MOS transistor (reduction of thechannel length and oxide thickness) leads to the presence ofhigher electric fields, which are the source of degradationand lifetime reduction of the MOS transistor. In this context,a new reliability approach is needed. The work methodologyconsists in characterize and model the device before andafter ageing. Thereafter, we compare the degradedparameters (static, dynamic and RF) according to the appliedstress.II.DEVICE EXPERIMENTAL CHARACTERIZATION ANDPARAMETERS EXTRACTIONIt is essential to characterize power RF LDMOS in orderto extract parameters before and after device stress. This stepwould enable us to correlate ageing test to any parameterdrift, or even to help identify a degradation phenomenon. Acommercial Philips power RF LDMOS (L g =0.8µm) has beenused for this study. The main characteristics of this devicecan be listed as follows: frequencies up to 2 GHz, outputpower of 10 Watts, breakdown voltage of 75V. I-V, C-V andS-parameters measurements were performed, respectively,by an Agilent E5270 DC analyzer, HP 4194 impedanceanalyser and an Agilent E8362B Network Analyzer, pilotedby IC-CAP Agilent software.To quantify the parameter shift that appears after ageing,a new electro-thermal model was used for power RFLDMOS devices as a reliability tool [2]. It has beenimplemented in Agilent’s ADS software using SymbolicDefined Device (SDD), by providing a more accurate andflexible model. For simplicity, the new IC-CAP plotoptimizer feature was applied instead of direct modelparameter extraction. For each test condition, ten sampleshave been used to ensure the reproducibility of the results(error bars less than 2%).III. THERMAL BENCH AND ACCELERATED AGEINGCONDITIONSIn our experiments, the devices are stressed with anapplied drain-source voltage (V ds ) of 40V and a gate-sourcevoltage (V gs ) necessary to obtain a permanent drain-sourcecurrent (I ds ) less than 20 mA (without self-heating effect),which corresponds to the quiescent current at ambienttemperature. The accelerated ageing tests were performedwith a THERMONICS T-2820 Precision TemperatureForcing System (PTFS); the system is designed for troublefreetemperature testing of electronic components (for TST:Thermal Shock Tests and TCT: Thermal Cycling Tests), anda SUN SYSTEM EC11 thermal environmental chamber (forHTSL: High Temperature Storage Life). These equipmentsare easily monitored via the IEEE-488 remote interfaces andpiloted by Labview software.This bench designed to apply electrical and/or thermalstress to RF LDMOS devices is currently implemented. Fourkinds of accelerated ageing tests (TST and TCT with andwithout DC bias, HVD: V ds =40V, V gs =3.5V, 15h, andHTSL) were performed. A cycle consists in starting atambient room temperature (T amb ), proceeding to cold (T min ),then to hot (T max ), or alternately proceeding to hot, then tocold, without interruption. For TST, the total transfer time©EDA Publishing/THERMINIC 2008 123ISBN: 978-2-35500-008-9